View EL5420TISZ_4876442.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
EL5420T
Data Sheet September 25, 2009 FN6838.0
12MHz Rail-to-Rail Input-Output Operational Amplifier
The EL5420T is a low power, high voltage rail-to-rail input-output amplifier. The EL5420T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from 4.5V to 19V. It can be configured for single or dual supply operation, and typically consumes only 500A per amplifier. The EL5420T has an output short circuit capability of 200mA and a continuous output current capability of 70mA. The EL5420T features a slew rate of 12V/s. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL5420T an ideal amplifier solution for use in TFT-LCD panels as a VCOM or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL5420T is available in a 14 Ld TSSOP package, 14 Ld SOIC package, and a space saving thermally enhanced 16 Ld QFN package. All feature a standard operational amplifier pin out. The devices operate over an ambient temperature range of -40C to +85C.
Features
* 12MHz (-3dB) Bandwidth * 4.5V to 19V Maximum Supply Voltage Range * 12V/s Slew Rate * 500A Supply Current (per Amplifier) * 70mA Continuous Output Current * 200mA Output Short Circuit Current * Unity-gain Stable * Beyond the Rails Input Capability * Rail-to-rail Output Swing * Built-in Thermal Protection * -40C to +85C Ambient Temperature Range * Pb-free (RoHS compliant)
Applications
* TFT-LCD Panels * VCOM Amplifiers * Static Gamma Buffers * Electronics Notebooks * Electronics Games * Touch-screen Displays * Personal Communication Devices
Ordering Information
PART NUMBER (Note) EL5420TILZ* EL5420TIRZ* EL5420TISZ* PART MARKING 5420TIL Z 5420TIR Z 5420TIS Z PACKAGE (Pb-Free) 16 Ld QFN 14 Ld TSSOP 14 Ld SOIC PKG. DWG. # MDP0046 MDP0044 MDP0027
* Personal Digital Assistants (PDA) * Portable Instrumentation * Sampling ADC Amplifiers * Wireless LANs * Office Automation * Active Filters * ADC/DAC Buffer
*Add "-T7" or "-T13" suffix for tape and reel.Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5420T Pinouts
EL5420T (16 LD QFN) TOP VIEW
14 VOUTD 15 VOUTA
EL5420T (14 LD TSSOP, SOIC) TOP VIEW
VOUTA 1 13 NC VINA- 2 12 VINDVINA+ 3 VS+ 4 VINB+ 5 VINB- 6 VOUTB 7 -+ +-+ +14 VOUTD 13 VIND12 VIND+ 11 VS10 VINC+ 9 VINC8 VOUTC
VINA- 1 VINA+ 2 VS+ 3 VINB+ 4 VINB- 5 VOUTB 6 VOUTC 7 VINC- 8 THERMAL PAD
16 NC
11 VIND+ 10 VS9 VINC+
THERMAL PAD CONNECTS TO VS-
2
FN6838.0 September 25, 2009
EL5420T
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V Input Voltage Range (VINx+, VINx-) . . . . . . . . . VS- -0.5V, VS+ +0.5V Input Differential Voltage (VINx+ - VINx-) . . .(VS+ +0.5V)-(VS- -0.5V) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . 70mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V
Thermal Information
Thermal Resistance Junction-to-Ambient (Typical) 16 Ld QFN (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ld SOIC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 14 Ld TSSOP (Note 2) . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Junction-to-Case (Typical) JA (C/W) 47 88 100 JC (C/W)
16 Ld QFN (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Power Dissipation Curves . . . . . . . . . . . . . . .See Figures 30 and 31 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS
VS+ = +5V, VS- = -5V, RL = 10k to 0V, TA = +25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 4)
VCM = 0V 14 LD TSSOP, SOIC package 16 LD QFN package
3 7 2 2 1 2 -5.5
13
mV V/C V/C
IB RIN CIN CMIR CMRR AVOL
Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open Loop Gain
VCM = 0V
50
nA G pF
+5.5 75 105
V dB dB
For VINx from -5.5V to +5.5V -4.5V VOUTx +4.5V
50 75
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = +5mA VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 -4.94 4.94 200 70 -4.85 V V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Amplifier) Power Supply Rejection Ratio VCM = 0V, No load Supply is moved from 2.25V to 9.5V 60 4.5 500 75 19 750 V A dB
DYNAMIC PERFORMANCE SR Slew Rate (Note 5) -4.0V VOUTx +4.0V, 20% to 80% 12 V/s
3
FN6838.0 September 25, 2009
EL5420T
Electrical Specifications
PARAMETER tS BW GBWP PM CS VS+ = +5V, VS- = -5V, RL = 10k to 0V, TA = +25C, unless otherwise specified. (Continued) CONDITIONS AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF f = 5MHz MIN TYP 500 12 8 50 75 MAX UNIT ns MHz MHz dB
DESCRIPTION Settling to +0.1% (Note 6) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS
VS+ = +5V, VS- = 0V, RL = 10k to 2.5V, TA = +25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift (Note 4)
VCM = 2.5V 14 LD TSSOP, SOIC package 16 LD QFN package
3 7 2 2 1 2 -0.5
13
mV V/C V/C
IB RIN CIN CMIR CMRR AVOL
Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open Loop Gain
VCM = 2.5V
50
nA G pF
+5.5 70 105
V dB dB
For VINx from -0.5V to +5.5V 0.5V VOUTx + 4.5V
45 75
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -2.5mA IL = +2.5mA VCM = 2.5V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 4.85 30 4.97 125 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Amplifier) Power Supply Rejection Ratio VCM = 2.5V, No load Supply is moved from 4.5V to 19V 60 4.5 500 75 19 750 V A dB
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS Slew Rate (Note 5) Settling to +0.1% (Note 6) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUTx 4V, 20% to 80% AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF f = 5MHz 12 500 12 8 50 75 V/s ns MHz MHz dB
4
FN6838.0 September 25, 2009
EL5420T
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS Input Offset Voltage Average Offset Voltage Drift (Note 4) VCM = 9V 14 LD TSSOP, SOIC package 16 LD QFN package IB RIN CIN CMIR CMRR AVOL Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open Loop Gain For VINx from -0.5V to +18.5V 0.5V VOUTx 17.5V -0.5 53 75 78 90 VCM = 9V 4 7 2 2 1 2 +18.5 50 15 mV V/C V/C nA G pF V dB dB VS+ = +18V, VS- = 0V, RL = 10k to 9V, TA = +25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -9mA IL = +9mA VCM = 9V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ 17.85 100 17.90 200 70 150 mV V mA mA
POWER SUPPLY PERFORMANCE (VS+) - (VS-) IS PSRR Supply Voltage Range Supply Current (Per Amplifier) Power Supply Rejection Ratio VCM = 9V, No load Supply is moved from 4.5V to 19V 60 4.5 550 75 19 750 V A dB
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS NOTES: 4. Measured over -40C to +85C ambient operating temperature range. See the typical TCVOS production distribution shown in the "Typical Performance Curves" on page 6 5. Typical slew rate is an average of the slew rates measured on the rising (20%-80%) and the falling (80%-20%) edges of the output signal. 6. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a 0.1% error band. The range of the error band is determined by: Final Value(V)[Full Scale(V)*0.1%] Slew Rate (Note 5) Settling to +0.1% (Note 6) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUTx 17V, 20% to 80% AV = +1, VOUTx = 2V step, RL= 10k, CL= 8pF RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF AV = -50, RF = 5k, RG= 100 RL= 10k, CL= 8pF f = 5MHz 12 500 12 8 50 75 V/s ns MHz MHz dB
5
FN6838.0 September 25, 2009
EL5420T Typical Performance Curves
3200 QUANTITY (AMPLIFIERS) 2800 2400 2000 1600 1200 800 400 0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 INPUT OFFSET VOLTAGE (mV) 35 QUANTITY (AMPLIFIERS) VS = 5V TA = +25C TYPICAL PRODUCTION DISTRIBUTION 30 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 INPUT OFFSET VOLTAGE DRIFT (|V|/C) VS = 5V -40C TO +85C TYPICAL PRODUCTION DISTRIBUTION
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (TSSOP, SOIC)
30 QUANTITY (AMPLIFIERS) 25 20 15 10 5 0 0 VS = 5V -40C to +85C
7.5 INPUT OFFSET VOLTAGE (mV) TYPICAL PRODUCTION DISTRIBUTION VS = 5V 5.0
2.5
0.0
1 2 3 4 5 6 7 8 9 10 11 12 INPUT OFFSET VOLTAGE DRIFT (|V|/C)
-2.5 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (QFN)
FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE
2 OUTPUT HIGH VOLTAGE (V) INPUT BIAS CURRENT (nA) VS = 5V 1
4.95 VS = 5V IOUT = 5mA 4.93
0
4.91
-1
-2 -50
0
50 100 TEMPERATURE (C)
150
4.89 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE
6
FN6838.0 September 25, 2009
EL5420T Typical Performance Curves
-4.91 OUTPUT LOW VOLTAGE (V) -4.92 -4.93 -4.94 -4.95 -4.96 -50 OPEN LOOP GAIN (dB) VS = 5V IOUT = -5mA
(Continued)
140 120 100 80 60 40 -50 VS = 5V RL = 10k
0
50 100 TEMPERATURE (C)
150
0
50 100 TEMPERATURE (C)
150
FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE
13.5 V S = 5V R L = 10k SLEW RATE (V/s) 13.0
550 SUPPLY CURRENT (A) VS = 5V NO LOAD INPUTS AT GND
525
500
12.5
475
12.0 -50
0
50 100 TEMPERATURE (C)
150
450 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 9. SLEW RATE vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE
650 SUPPLY CURRENT (A) 600 550 500 450 400 350 2 4 6 8 SUPPLY VOLTAGE (V) 10 TA = +25C SLEW RATE (V/s)
16
14
TA = +25C AV = 1 RL = 10k CL = 8pF
12
10
8
2
6 8 4 SUPPLY VOLTAGE (V)
10
FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE
FIGURE 12. SLEW RATE vs SUPPLY VOLTAGE
7
FN6838.0 September 25, 2009
EL5420T Typical Performance Curves
100 OPEN LOOP GAIN (dB) 80 GAIN PHASE () GAIN (dB) 60 40 20 0 -20 10 PHASE VS = 5V TA = +25C RL = 10k CL = 8pF 100 1k 10k 100k 1M 10M 150 100 50 0 -50 100M
(Continued)
250 200 0 5 10k 1k 560 -5 150
-10
VS = 5V AV = 1 CL = 8pF 1M 10M FREQUENCY (Hz) 100M
-15 100k
FREQUENCY (Hz)
FIGURE 13. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS RL
20 100pF 10 GAIN (dB) 0 -10 1000pF -20 VS = 5V AV = 1 RL = 10k -30 100k 50pF OUTPUT IMPEDANCE ()
200 160 120 80 40 0 VS = 5V AV = 1 RL = OPEN VOUTx = +13dBm
8pF
1M 10M FREQUENCY (Hz)
100M
1k
10k
100k 1M FREQUENCY (Hz)
10M
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 16. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY
MAXIMUM OUTPUT SWING (VP-P)
12 10 CMRR (dB) 8 6 4 2 0
0 -10 -20 -30 -40 -50 -60 100k 1M FREQUENCY (Hz) 10M -70 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M VS = 5V TA = +25C VINx = -10dBm
VS = 5V TA = +25C AV = 1 RL = 10k CL = 8pF
10k
FIGURE 17. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 18. CMRR vs FREQUENCY
8
FN6838.0 September 25, 2009
EL5420T Typical Performance Curves
0 VOLTAGE NOISE (nV/Hz) -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 1k PSRR+ PSRR10k 100k 1M FREQUENCY (Hz) 10M VS = 5V TA = +25C
(Continued)
1000 TA = +25C
100
10
1 100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 19. PSRR vs FREQUENCY
FIGURE 20. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY
0.050 0.045 0.040 THD+N (%) 0.035 0.030 0.025 0.020 0.015 0.010 0.005 100 1k 10k FREQUENCY (Hz) 100k VS = 5V RL = 10k AV = 1 VIN = 1.4VRMS
-60
-70 XTALK(dB)
MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION
-80
VS = 5V AV = 1 VINx = 0dBm
-90
-100
10k
100k 1M FREQUENCY (Hz)
10M
FIGURE 21. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
FIGURE 22. CHANNEL SEPARATION vs FREQUENCY RESPONSE
100 80 OVERSHOOT (%) 60 40 20 0 10 STEP SIZE (V)
5 4 3 2 1 0 -1 -2 -3 -4 1000 -5 100
VS = 5V TA = +25C AV = 1 RL = 10k CL = 8pF
0.1%
VS = 5V TA = +25C AV = 1 RL = 10k VINx = 50mV 100 LOAD CAPACITANCE (pF)
0.1%
200
300 400 500 SETTLING TIME (ns)
600
700
FIGURE 23. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE
FIGURE 24. STEP SIZE vs SETTLING TIME
9
FN6838.0 September 25, 2009
EL5420T Typical Performance Curves
(Continued)
50mV/DIV
1V/DIV
VS = 5V TA = +25C AV = 1 RL= 10k CL =8pF
VS = 5V TA = +25C AV = 1 RL= 10k CL =8pF
200ns/DIV 100mV STEP 6V STEP 1s/DIV
FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE
EL5420T (14LD TSSOP/SOIC shown)
1 CLA RLA 0 2 VINAVIND- 13 VOUTA VOUTD 14 0 RLD CLD
VOUTA
VOUTD
VINA+
49.9
3
VINA+
VIND+
12 49.9
VIND+ VS+ 4.7F
VS+
+ 4.7F 0.1F
4
Vs+
Vs-
11 0.1F
VINB+
49.9 0
5
VINB+
VINC+
10
VINC+
49.9 0
6
VINB-
VINC-
9
VOUTB
CLB RLB
7
VOUTB
VOUTC
8 RLC CLC
VOUTC
FIGURE 27. BASIC TEST CIRCUIT
Pin Descriptions
EL5420T 14 LD TSSOP, 14 LD SOIC 1 2 3 4 5 6 7 8 9 16 LD QFN 15 1 2 3 4 5 6 7 8 PIN NAME VOUTA VINAVINA+ VS+ VINB+ VINBVOUTB VOUTC VINCFUNCTION Amplifier A Output Amplifier A Inverting Input Amplifier A Non-Inverting Input Positive Power Supply Amplifier B Non-Inverting Input Amplifier B Inverting Input Amplifier B Output Amplifier C Output Amplifier C Inverting Input (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) EQUIVALENT CIRCUIT (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2)
10
FN6838.0 September 25, 2009
EL5420T Pin Descriptions (Continued)
EL5420T 14 LD TSSOP, 14 LD SOIC 10 11 12 13 14 16 LD QFN 9 10 11 12 14 13, 16 pad PIN NAME VINC+ VSVIND+ VINDVOUTD NC Thermal Pad FUNCTION Amplifier C Non-Inverting Input Negative Power Supply Amplifier D Non-Inverting Input Amplifier D Inverting Input Amplifier D Output No Connect Functions as a heat sink. Connects to most negative potential, VS(Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) EQUIVALENT CIRCUIT (Reference Circuit 2)
VS+
VS+
VOUTx VINx VSVS-
GND
CIRCUIT 1
CIRCUIT 2
11
FN6838.0 September 25, 2009
EL5420T Applications Information
Product Description
The EL5420T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5420T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability, and is unity gain stable. The EL5420T features a slew rate of 12V/s. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage.
1V/DIV VS = 2.5V, TA = +25C, AV = 1, VINx = 6VP-P, RL = 10k to GND
OUTPUT
INPUT
100s/DIV
FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT
Operating Voltage, Input and Output Capability
The EL5420T can operate on a single supply or dual supply configuration. The EL5420T operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a standard 5V (or 2.5V) supply voltage to dip to -10%, or a standard 18V (or 9V) to rise by +5.5% without affecting performance or reliability. The input common-mode voltage range of the EL5420T extends 500mV beyond the supply rails. Also, the EL5420T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 28 shows the input voltage driven 500mV beyond the supply rails and the device output swinging between the supply rails. The EL5420T output typically swings to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 29 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.9VP-P. Refer to the "Electrical Specifications" Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the "Typical Performance Curves" on page 6.
5V/DIV VS = 5V, TA = +25C, AV = 1, VINx = 10VP-P, RL = 10k to GND
100s/DIV
FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND
Output Current
The EL5420T is capable of output short circuit currents of 200mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to 200mA (typical). To maintain maximum reliability the continuous output current should never exceed 70mA. This 70mA limit is determined by the characteristics of the internal metal interconnects. Also, see "Power Dissipation" on page 13 for detailed information on ensuring proper device operation and reliability for temperature and load conditions.
Unused Amplifiers
It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground.
Thermal Shutdown
The EL5420T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +165C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by 15C (typical) the device automatically turns
12
FN6838.0 September 25, 2009
OUTPUT
INPUT
EL5420T
ON the outputs by putting them in a low impedance (normal) operating state. where: * i = 1 to 4 (1, 2, 3, 4 corresponds to Channel A, B, C, D respectively) * VS = Total supply voltage (VS+ - VS-) * VS+ = Positive supply voltage * VS- = Negative supply voltage * ISMAX = Maximum supply current per amplifier (ISMAX = EL5420T quiescent current / 4) * VOUT = Output voltage * ILOAD = Load current Device overheating can be avoided by calculating the minimum resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD set the two PDMAX equations equal to each other and solve for VOUT/ILOAD. Reference the package power dissipation curves, Figures 30 and 31, for further information.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.2
Driving Capacitive Loads
As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL5420T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL5420T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1 to 10). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5420T amplifiers, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL5420T in the application. Proper load conditions will ensure that the EL5420T junction temperature stays within a safe operating region. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
1.04W
1.0 Power Dissipation (W) 0.8 0.6 0.4 0.2 0.0 0 25
SOIC14 JA = 120C/W QFN16 JA = 130C/W
962mW 833mW
TSSOP14 JA = 150C/W 85 100
(EQ. 1)
50
75
125
150
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation allowed The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
3.0
Am bie nt Te m pe ra ture (C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
2.66W
2.5 Power Dissipation (W) 2.0 1.5 1.0 0.5 0.0 0 25
QFN16 JA = 47C/W SOIC14 JA = 88C/W TSSOP14 JA = 100C/W
1.42W 1.25W
(EQ. 2)
when sourcing, and:
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3)
50
75
85 100
125
150
when sinking,
Am b ie n t T e m p e ra tu re (C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
13
FN6838.0 September 25, 2009
EL5420T
Power Supply Bypassing and Printed Circuit Board Layout
The EL5420T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the VS- pin is connected to ground) a 4.7F capacitor should be placed from VS+ to ground, then a parallel 0.1F capacitor should be connected as close to the amplifier as possible. One 4.7F capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground. For the QFN package, with exposed thermal pad, the pad should be connected to the lowest potential, VS-, to optimize thermal and operating performance. PCB vias should be placed below the device's exposed thermal pad to transfer heat to the VS- plane and away from the device.
Revision History
DATE 9/25/09 REVISION FN6838.0 Initial Release CHANGE
14
FN6838.0 September 25, 2009
EL5420T Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL Ao
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L
0.010
4(R)
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
15
FN6838.0 September 25, 2009
EL5420T QFN (Quad Flat No-Lead) Package Family
A D N (N-1) (N-2) B
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL QFN44 QFN38 A 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 0.90 0.02 0.22 0.20 5.00 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5
1 2 3
A1
PIN #1 I.D. MARK E
b c D D2 E
(N/2)
5.80 3.60/2.48 8.00 6.00
2X 0.075 C
E2
2X 0.075 C
5.80 4.60/3.40 0.80 0.53 32 8 8 0.50 0.50 32 7 9
e L N ND
TOP VIEW N LEADS
0.10 M C A B (N-2) (N-1) N b
NE
L
PIN #1 I.D. 3 1 2 3
MILLIMETERS SYMBOL QFN28 QFN24 A A1 b c 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7 QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5 QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4
TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5
(E2)
NE 5 (N/2)
D D2
(D2) BOTTOM VIEW
7
E E2 e L
e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD
0.10 C
N ND NE
Rev 11 2/07
SEE DETAIL "X" SIDE VIEW
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.
(c) C A
2
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.
(L) A1 DETAIL X N LEADS
16
FN6838.0 September 25, 2009
EL5420T Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE A A1 A2
0.20 C B A
PIN #1 I.D. E E1
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
1 B TOP VIEW
(N/2)
2X N/2 LEAD TIPS
b c D E E1
C SEATING PLANE
e
0.05
H
e L L1
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL Au
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0x - 8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6838.0 September 25, 2009

▲Up To Search▲

Price & Availability of EL5420TISZ

	To Download EL5420TISZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .